An electronic component such as a semiconductor chip is mounted on a wiring substrate. To increase the density of wiring patterns, a known buildup process is performed by alternately stacking wiring layers and insulation layers. Japanese Laid-Open Patent Publication No. 2015-191968 describes an example of such type of a wiring substrate. In the wiring substrate described in the publication, a high-density wiring layer that includes an insulation layer formed from a photosensitive resin is laminated on a low-density wiring layer that includes an insulation layer formed from a thermosetting resin.
FIG. 15 illustrates one example of a wiring substrate in the related art. A wiring substrate 200 includes a low-density wiring layer 201, a solder resist layer 202 formed on the lower surface of the low-density wiring layer 201, and a high-density wiring layer 203 formed on the upper surface of the low-density wiring layer 201. The low-density wiring layer 201 has a structure obtained by sequentially laminating a wiring layer 211, an insulation layer 212, a wiring layer 213, an insulation layer 214, a wiring layer 215, and an insulation layer 216. The insulation layers 212, 214, and 216 are formed from an insulative resin of which the main component is a thermosetting resin. The high-density wiring layer 203 has a structure obtained by sequentially laminating a wiring layer 220, an insulation layer 221, a wiring layer 222, an insulation layer 223, a wiring layer 224, an insulation layer 225, and a wiring layer 226 on the upper surface of the insulation layer 216. The insulation layers 221, 223, and 225 are formed from an insulative resin of which the main component is a photosensitive resin.
The wiring substrate 200 does not include a core substrate (support substrate) that is highly rigid and thicker than the insulation layers 212, 214, 216, and the like. This allows the wiring substrate 200 to be entirely reduced in thickness.